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integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 1 preliminary information rev. 00b 05/23/02 is71v08f32 x s08 is71v16f32 x s08 issi ? issi reserves the right to make changes this specification herein and it products at any time without notice. issi assumes no responsibility or liability arising out of the application or use of any information, product or services described herein. customers are advised to obtain the latest version of this device specification before re lying on any published information and before placing orders for products. ? copyright 2002, integrated silicon solution, inc. 3.0 volt-only flash & sram combo with stacked multi-chip package (mcp) ? 32 mbit simultaneous operation flash memory and 8 mbit static ram preliminary information may 2002 mcp features ? power supply voltage 2.7v to 3.3v high performance: flash: 70ns maximum access time sram: 70ns maximum access time package: 73-ball bga - 32 mbit flash/8 mbit sram operating temperature: -40c to +85c flash features power dissipation: read current at 1 mhz: 7 ma maximum read current at 5 mhz: 18 ma maximum sleep mode: 5 a maximum simultaneous read and write operations: zero latency between read and write operations; data can be programmed or erased in one bank while data is simultaneously being read from the other bank low-power mode: a period of no activity causes flash to enter a low-power state erase suspend/resume: suspends of erase activity to allow a read in the same bank sector erase architecture: 8 words of 4k size and 63 words of 32k size (32 mbit) any combination of sectors, or the entire flash can be simultaneously erased erase algorithms: automatically preprograms/erases the flash memory entirely, or by sector program algorithms: automatically writes and verifies data at specified address hidden rom region: 64kb with a factory-serialized secure electronic serial number (esn), which is accessible through a command sequence data polling and toggle bit: allow for detection of program or erase cycle completion ready-busy output (ry/ by ): detection of program or erase cycle completion over 100,000 write/erase cycles low supply voltage (vccf 2.5v) inhibits writes wp /acc input pin: if v il , allows protection of boot sectors if v ih , allows removal of boot sector protection if vacc, program time is reduced by 40% boot sector: top or bottom sram features (8 mb density) power dissipation: operating: 25 ma maximum standby: 15 a maximum chip selects: ce1 s, ce2s power down feature using ce1s , or ce2s or lb s & ub s data retention supply voltage: 1.0 to 3.3 volt byte data control: lb s (dq0?dq7), ub s (dq8?dq15) ? on x16 version general description the flash and sram mcp is available in 32 mbit flash/8 mbit sram having a data bus of either x8 or x16. the 32 mbit flash is composed of 2,097,152 words of 16 bits or 4,194,304 bytes of 8 bits. data lines dq0-dq7 handle the x8 format, while lines dq0-dq15 handle the x16 format. the package uses a 3.0v power supply for all operations. no other source is required for program and erase operations. the flash can be programmed in system using this 3.0v supply, or can be programmed in a standard eprom programmer. the 32 mbit flash/8 mbit sram is offered in a 73-pin bga package. the flash is compatible with the jedec flash command set standard . the flash access time is 70 ns and the sram access time is 70ns. the flash architecture is composed of two banks which allows simultaneous operation on each. optimized performance can be achieved by first initializing a program or erase function in one bank, then immediately starting a read from the other bank. both operations would then be operating simultaneously, with zero latency.
2 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 logic symbol gnd gnd v ccf ry/ by 8mb static ram 32mb flash memory dq0-dq15/a-1 a0-a20 a-1 wp /acc reset ce f i/of sa lb s ub s we oe ce1 s ce2s dq0-dq15 a0-a18 v ccs mcp block diagram a0-a20, a-1 sa ce f ce1 s ce2s oe we wp /acc reset ub s lb s i/of dq0-dq15 22 16 or 8 ry/ by
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 3 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 state control & command register reset we ce byte wp /acc dq0-dq15 a0-a20 a0-a20 a0-a20 a0-a20 a0-a20 lower bank address upper bank address y -decoder latches and control logic lower bank upper bank x-decoder y -decoder latches and control logic x-decoder status control dq0-dq15 dq0-dq15 dq0-dq15 oe byte oe byte v cc gnd ry/ by flash memory block diagram
4 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 12345678901234 1 234567890123 4 1 234567890123 4 1 234567890123 4 1 234567890123 4 12345678901234 pin descriptions a0-a18 addr ess inputs, common a19-a20, a-1 address inputs, flash dq0-dq15/a-1 data inputs/outputs reset reset ce1 s, ce2s chip selects, sram i/of i/o configuration, flash ce f chip enable input, flash oe output enable input we write enable input lb s lower-byte control(dq0-dq7), sram ub s upper-byte control (dq8-dq15), sram wp /acc write protect/acceleration pin, flash ry/ by ready/busy output sa high order address pin, sram (x8) nc no connection vccf power, flash vccs power, sram gnd ground 123456789012345 1 2345678901234 5 1 2345678901234 5 1 2345678901234 5 1 2345678901234 5 123456789012345 12345678901234 1 234567890123 4 1 234567890123 4 1 234567890123 4 1 234567890123 4 12345678901234 123456789012345 1 2345678901234 5 1 2345678901234 5 1 2345678901234 5 1 2345678901234 5 123456789012345 12345678901234 1 234567890123 4 1 234567890123 4 1 234567890123 4 1 234567890123 4 12345678901234 12345678901234 1 234567890123 4 1 234567890123 4 1 234567890123 4 1 234567890123 4 12345678901234 pin configuration (32 mb flash and 8 mb sram) 73 ball fbga (top view) 12345678910 anc nc bncncncnc cnc a7 lb wp /acc we a8 a11 da3a6 ub reset ce2s a19 a12 a15 e a2 a5 a18 ry/ by a20 a9 a13 nc f nc a1 a4 a17 a10 a14 nc nc g nc a0 gnd dq1 dq6 sa a16 nc h ce f oe dq9 dq3 dq4 dq13 dq15/a-1 i/of j ce1 s dq0 dq10 v cc fv cc s dq12 dq7 gnd k dq8 dq2 dq11 nc dq5 dq14 lncncncnc mnc nc 1234 1 23 4 1 23 4 1234 shared flash only sram only
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 5 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 operation (1,3) ce f ce 1s ce2s oe we sa (6) lb s ub sdq 0- dq 7 dq 8 -dq 15 reset wp /acc (5) full standby h h x x xxxx high-z high-z h x hxlx xxxx high-z high-z h x output disable h l h h h x x x high-z high-z h x h l h x x x h h high-z high-z h x l h x h h x x x high-z high-z h x l x l h h x x x high-z high-z h x read from flash (2) lhxl hxxx d out d out hx lxl l hxxx d out d out hx write to flash l h x h l x x x d in d in hx lxlh lxxx d in d in hx read from sram h l h l h x l l d out d out hx h l h l h x h l high-z d out hx hlhlhxlhd out high-z h x write to sram h l h x l x l l d in d in hx h l h x l x h l high-z d in hxhl hxlxlhd in high-z h x temporary sector x x x x xxxx x x v id x group unprotection (4) flash hardware x h x x xxxx high-z high-z l x re- set xxlx xxxx high-z high-z l x boot block sector x x x x xxxx x x x l write protection notes: 1. any operations not indicated this column are inhibited. 2. we can be vil if oe is vil, oe at vih initiates the write operations. 3. do not apply ce f = vil, ce 1s = vil and ce2s = vih all at once. 4. it is also used for the extended sector group protections. 5. wp /acc = vil: protection of boot sectors. wp /acc = vih: removal of boot sectors protection. wp /acc = vacc (9v): program time will reduce by 40%. 6. sa: don?t care or open. 7. l = vil, h = vih, x = vil or vih. device bus operations user bus operations (flash=word mode: i/of = vccf, sram= x16 version)
6 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 operation ( ce ce1 ce2s dq 15 /a-1 oe we sa (6) lb ub dq 0- dq 7 dq 8 -dq 15 reset wp/acc (5) full standby h h x x x x x x x high-z high-z h x h x l x x x x x x high-z high-z h x output disable h l h x h h x x x high-z high-z h x h l h x x x x h h high-z high-z h x l h x a-1 h h x x x high-z high-z h x l x l a-1 h h x x x high-z high-z h x read from flash (2) l h x a-1 l h x x x d out d out hx l x l a-1 l h x x x d out d out hx write to flash l h x a-1 h l x x x d in d in hx l x l a-1 h l x x x d in d in hx read from sram h l h x l h x l l d out d out hx h l h x l h x h l high-z d out hx hlh xlhxlh d out high-z h x write to sram h l h x x l x l l d in d in hx h l h x x l x h l high-z d in hx hlh xxlxlh d in high-z h x temporary sector x x x x x x x x x x x v id x group unprotection (4) flash hardware x h x x x x x x x high-z high-z l x reset x x l x x x x x x high-z high-z l x boot block sector x x x x x x x x x x x x l write protection notes: 1. any operations not indicated this column are inhibited. 2. we can be vil if oe is vil, oe at vih initiates the write operations. 3. do not apply ce f = vil, ce 1s = vil and ce2s = vih all at once. 4. it is also used for the extended sector group protections. 5. wp /acc = vil: protection of boot sectors. wp /acc = vih: removal of boot sectors protection. wp /acc = vacc (9v): program time will reduce by 40%. 6. lb s, ub s: don?t care or open. 7. l = vil, h = vih, x = vil or vih. device bus operations user bus operations (flash=byte mode: i/of = gnd, sram= x16 version)
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 7 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 operation (1,3) ce f ce 1s ce2s oe we sa (6) lb s ub sdq 0- dq 7 dq 8 -dq 15 reset wp /acc (5) full standby h h x x xxxx high-z high-z h x hxlx xxxx high-z high-z h x output disable h l h h h x x x high-z high-z h x h l h x x x h h high-z high-z h x l h x h h x x x high-z high-z h x l x l h h x x x high-z high-z h x read from flash (2) lhxl hxxx d out d out hx lxl l hxxx d out d out hx write to flash l h x h l x x x d in d in hx lxlh lxxx d in d in hx read from sram h l h l h sa x x d out high-z h x write to sram h l h x l sa x x d in high-z h x temporary sector x x x x xxxx x x v id x group unprotection (4) flash hardware x h x x xxxx high-z high-z l x reset x x l x xxxx high-z high-z l x boot block sector x x x x xxxx x x x l write protection device bus operations user bus operations (flash=word mode: i/of = vccf, sram= x8 version) notes: 1. any operations not indicated this column are inhibited. 2. we can be vil if oe is vil, oe at vih initiates the write operations. 3. do not apply ce f = vil, ce 1s = vil and ce2s = vih all at once. 4. it is also used for the extended sector group protections. 5. wp /acc = vil: protection of boot sectors. wp /acc = vih: removal of boot sectors protection. wp /acc = vacc (9v): program time will reduce by 40%. 6. lb s, ub s: don?t care or open. 7. l = vil, h = vih, x = vil or vih.
8 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 notes: 1. any operations not indicated this column are inhibited. 2. we can be vil if oe is vil, oe at vih initiates the write operations. 3. do not apply ce f = vil, ce 1s = vil and ce2s = vih all at once. 4. it is also used for the extended sector group protections. 5. wp /acc = vil: protection of boot sectors. wp /acc = vih: removal of boot sectors protection. wp /acc = vacc (9v): program time will reduce by 40%. 6. lb s, ub s: don?t care or open. 7. l = vil, h = vih, x = vil or vih. device bus operations user bus operations (flash=byte mode: i/of = gnd, sram= x8 version) op- eration ( ce ce1 ce2s dq 15 /a-1 oe we sa (6) lb ub dq 0- dq 7 dq 8 -dq 15 reset wp/acc (5) full standby h h x x x x x x x high-z high-z h x h x l x x x x x x high-z high-z h x output disable h l h x h h x x x high-z high-z h x h l h x x x x h h high-z high-z h x l h x a-1 h h x x x high-z high-z h x l x l a-1 h h x x x high-z high-z h x read from flash (2) l h x a-1 l h x x x d out d out hx l x l a-1 l h x x x d out d out hx write to flash l h x a-1 h l x x x d in d in hx l x l a-1 h l x x x d in d in hx read from sram h l h x l h sa x x d out high-z h x write to sram h l h x x l sa x x d in high-z h x temporary sector x x x x x x x x x x x v id x group unprotection (4) flash hardware x h x x x x x x x high-z high-z l x re- set x x l x x x x x x high-z high-z l x boot block sector x x x x x x x x x x x x l write protection
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 9 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 flash - top boot sector address sector sector type c type b type a sector address size (x8) (x16) a20-a12 kb/kw address range address range bank2 bank2 bank2 sa0 000000xxx 64/32 000000h?00ffffh 000000h?07fffh bank2 bank2 bank2 sa1 000001xxx 64/32 010000h?01ffffh 008000h?0ffffh bank2 bank2 bank2 sa2 000010xxx 64/32 020000h?02ffffh 010000h?17fffh bank2 bank2 bank2 sa3 000011xxx 64/32 030000h?03ffffh 018000h?01ffffh bank2 bank2 bank2 sa4 000100xxx 64/32 040000h?04ffffh 020000h?027fffh bank2 bank2 bank2 sa5 000101xxx 64/32 050000h?05ffffh 028000h?02ffffh bank2 bank2 bank2 sa6 000110xxx 64/32 060000h?06ffffh 030000h?037fffh bank2 bank2 bank2 sa7 000111xxx 64/32 070000h?07ffffh 038000h?03ffffh bank2 bank2 bank2 sa8 001000xxx 64/32 080000h?08ffffh 040000h?047fffh bank2 bank2 bank2 sa9 001001xxx 64/32 090000h?09ffffh 048000h?04ffffh bank2 bank2 bank2 sa10 001010xxx 64/32 0a0000h?0affffh 050000h?057fffh bank2 bank2 bank2 sa11 001011xxx 64/32 0b0000h?0bffffh 058000h?05ffffh bank2 bank2 bank2 sa12 001100xxx 64/32 0c0000h?0cffffh 060000h?067fffh bank2 bank2 bank2 sa13 001101xxx 64/32 0d0000h?0dffffh 068000h?06ffffh bank2 bank2 bank2 sa14 001110xxx 64/32 0e0000h?0effffh 070000h?077fffh bank2 bank2 bank2 sa15 001111xxx 64/32 0f0000h?0fffffh 078000h?07ffffh bank2 bank2 bank2 sa16 010000xxx 64/32 100000h?10ffffh 080000h?087fffh bank2 bank2 bank2 sa17 010001xxx 64/32 110000h?11ffffh 088000h?08ffffh bank2 bank2 bank2 sa18 010010xxx 64/32 120000h?12ffffh 090000h?097fffh bank2 bank2 bank2 sa19 010011xxx 64/32 130000h?13ffffh 098000h?09ffffh bank2 bank2 bank2 sa20 010100xxx 64/32 140000h?14ffffh 0a0000h?0a7fffh bank2 bank2 bank2 sa21 010101xxx 64/32 150000h?15ffffh 0a8000h?0affffh bank2 bank2 bank2 sa22 010110xxx 64/32 160000h?16ffffh 0b0000h?0b7fffh bank2 bank2 bank2 sa23 010111xxx 64/32 170000h?17ffffh 0b8000h?0bffffh bank2 bank2 bank2 sa24 011000xxx 64/32 180000h?18ffffh 0c0000h?0c7fffh bank2 bank2 bank2 sa25 011001xxx 64/32 190000h?19ffffh 0c8000h?0cffffh bank2 bank2 bank2 sa26 011010xxx 64/32 1a0000h?1affffh 0d0000h?0d7fffh bank2 bank2 bank2 sa27 011011xxx 64/32 1b0000h-1bffffh 0d8000h-0dffffh bank2 bank2 bank2 sa28 011100xxx 64/32 1c0000h?1cffffh 0e0000h?0e7fffh bank2 bank2 bank2 sa29 011101xxx 64/32 1d0000h?1dffffh 0e8000h?0effffh
10 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 flash - top boot sector address continued: sector sector type c type b type a sector address size (x8) (x16) a20-a12 kb/kw address range address range bank2 bank2 bank2 sa30 011110xxx 64/32 1e0000h?1effffh 0f0000h?0f7fffh bank2 bank2 bank2 sa31 011111xxx 64/32 1f0000h?1fffffh 0f8000h?0fffffh bank1 bank2 bank2 sa32 100000xxx 64/32 200000h?20ffffh 100000h?107fffh bank1 bank2 bank2 sa33 100001xxx 64/32 210000h?21ffffh 108000h?10ffffh bank1 bank2 bank2 sa34 100010xxx 64/32 220000h?22ffffh 110000h?117fffh bank1 bank2 bank2 sa35 100011xxx 64/32 230000h?23ffffh 118000h?11ffffh bank1 bank2 bank2 sa36 100100xxx 64/32 240000h?24ffffh 120000h?127fffh bank1 bank2 bank2 sa37 100101xxx 64/32 250000h?25ffffh 128000h?12ffffh bank1 bank2 bank2 sa38 100110xxx 64/32 260000h?26ffffh 130000h?137fffh bank1 bank2 bank2 sa39 100111xxx 64/32 270000h?27ffffh 138000h?13ffffh bank1 bank2 bank2 sa40 101000xxx 64/32 280000h?28ffffh 140000h?147fffh bank1 bank2 bank2 sa41 101001xxx 64/32 290000h?29ffffh 148000h?14ffffh bank1 bank2 bank2 sa42 101010xxx 64/32 2a0000h?2affffh 150000h?157fffh bank1 bank2 bank2 sa43 101011xxx 64/32 2b0000h?2bffffh 158000h?15ffffh bank1 bank2 bank2 sa44 101100xxx 64/32 2c0000h?2cffffh 160000h?167fffh bank1 bank2 bank2 sa45 101101xxx 64/32 2d0000h?2dffffh 168000h?16ffffh bank1 bank2 bank2 sa46 101110xxx 64/32 2e0000h?2effffh 170000h?177fffh bank1 bank2 bank2 sa47 101111xxx 64/32 2f0000h?2fffffh 178000h?17ffffh bank1 bank1 bank2 sa48 110000xxx 64/32 300000h?30ffffh 180000h?187fffh bank1 bank1 bank2 sa49 110001xxx 64/32 310000h?31ffffh 188000h?18ffffh bank1 bank1 bank2 sa50 110010xxx 64/32 320000h?32ffffh 190000h?197fffh bank1 bank1 bank2 sa51 110011xxx 64/32 330000h?33ffffh 198000h?19ffffh bank1 bank1 bank2 sa52 110100xxx 64/32 340000h?34ffffh 1a0000h?1a7fffh bank1 bank1 bank2 sa53 110101xxx 64/32 350000h?35ffffh 1a8000h?1affffh bank1 bank1 bank2 sa54 110110xxx 64/32 360000h?36ffffh 1b0000h?1b7fffh bank1 bank1 bank2 sa55 110111xxx 64/32 370000h?37ffffh 1b8000h?1bffffh bank1 bank1 bank1 sa56 111000xxx 64/32 380000h?38ffffh 1c0000h?1c7fffh bank1 bank1 bank1 sa57 111001xxx 64/32 390000h?39ffffh 1c8000h?1cffffh bank1 bank1 bank1 sa58 111010xxx 64/32 3a0000h?3affffh 1d0000h?1d7fffh
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 11 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 note: the address range is a20:a-1 in byte mode (i/of=v il ) or a20:a0 in word mode (i/of=v ih ). the bank address bits are a20?a18 for type a, a20 and a19 for type b, and a20 for type c. device sector address size (x8) (x16) a20-a12 kb/kw address range address range typec type b type a 111111xxx 256/128 3fe000h-3fe0ffh 1ff000h-1ff07fh flash - top boot security sector addresses sector sector type c type b type a sector address size (x8) (x16) a20-a12 kb/kw address range address range bank1 bank1 bank1 sa59 111011xxx 64/32 3b0000h?3bffffh 1d8000h?1dffffh bank1 bank1 bank1 sa60 111100xxx 64/32 3c0000h?3cffffh 1e0000h?1e7fffh bank1 bank1 bank1 sa61 111101xxx 64/32 3d0000h?3dffffh 1e8000h?1effffh bank1 bank1 bank1 sa62 111110xxx 64/32 3e0000h?3effffh 1f0000h?1f7fffh bank1 bank1 bank1 sa63 111111000 8/4 3f0000h?3f1fffh 1f8000h?1f8fffh bank1 bank1 bank1 sa64 111111001 8/4 3f2000h?3f3fffh 1f9000h?1f9fffh bank1 bank1 bank1 sa65 111111010 8/4 3f4000h?3f5fffh 1fa000h?1fafffh bank1 bank1 bank1 sa66 111111011 8/4 3f6000h?3f7fffh 1fb000h?1fbfffh bank1 bank1 bank1 sa67 111111100 8/4 3f8000h?3f9fffh 1 fc000h?1fcfffh bank1 bank1 bank1 sa68 111111101 8/4 3fa000h?3fbfffh 1fd000h?1fdfffh bank1 bank1 bank1 sa69 111111110 8/4 3fc000h?3fdfffh 1fe000h?1fefffh bank1 bank1 bank1 sa70 111111111 8/4 3fe000h?3fffffh 1ff000h?1fffffh flash - top boot sector address continued:
12 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 sector type f type e typed sector address size (x8) (x16) a20-a12 kb/kw address range address range bank1 bank1 bank1 sa0 000000000 8/4 000000h?001fffh 000000h?000fffh bank1 bank1 bank1 sa1 000000001 8/4 002000h?003fffh 001000h?001fffh bank1 bank1 bank1 sa2 000000010 8/4 004000h?005fffh 002000h?002fffh bank1 bank1 bank1 sa3 000000011 8/4 006000h?007fffh 003000h?003fffh bank1 bank1 bank1 sa4 000000100 8/4 008000h?009fffh 004000h?004fffh bank1 bank1 bank1 sa5 000000101 8/4 00a000h?00bfffh 005000h?005fffh bank1 bank1 bank1 sa6 000000110 8/4 00c000h?00dfffh 006000h?006fffh bank1 bank1 bank1 sa7 000000111 8/4 00e000h?00ffffh 007000h?007fffh bank1 bank1 bank1 sa8 000001xxx 64/32 010000h?01ffffh 008000h?00ffffh bank1 bank1 bank1 sa9 000010xxx 64/32 020000h?02ffffh 010000h?017fffh bank1 bank1 bank1 sa10 000011xxx 64/32 030000h?03ffffh 018000h?01ffffh bank1 bank1 bank1 sa11 000100xxx 64/32 040000h?04ffffh 020000h?027fffh bank1 bank1 bank1 sa12 000101xxx 64/32 050000h?05ffffh 028000h?02ffffh bank1 bank1 bank1 sa13 000110xxx 64/32 060000h?06ffffh 030000h?037fffh bank1 bank1 bank1 sa14 000111xxx 64/32 070000h?07ffffh 038000h?03ffffh bank1 bank1 bank2 sa15 001000xxx 64/32 080000h?08ffffh 040000h?047fffh bank1 bank1 bank2 sa16 001001xxx 64/32 090000h?09ffffh 048000h?04ffffh bank1 bank1 bank2 sa17 001010xxx 64/32 0a0000h?0affffh 050000h?057fffh bank1 bank1 bank2 sa18 001011xxx 64/32 0b0000h?0bffffh 058000h?05ffffh bank1 bank1 bank2 sa19 001100xxx 64/32 0c0000h?0cffffh 060000h?067fffh bank1 bank1 bank2 sa20 001101xxx 64/32 0d0000h?0dffffh 068000h?06ffffh bank1 bank1 bank2 sa21 001110xxx 64/32 0e0000h?0effffh 070000h?077fffh bank1 bank1 bank2 sa22 001111xxx 64/32 0f0000h?0fffffh 078000h?07ffffh bank1 bank2 bank2 sa23 010000xxx 64/32 100000h?10ffffh 080000h?087fffh bank1 bank2 bank2 sa24 010001xxx 64/32 110000h?11ffffh 088000h?08ffffh bank1 bank2 bank2 sa25 010010xxx 64/32 120000h?12ffffh 090000h?097fffh bank1 bank2 bank2 sa26 010011xxx 64/32 130000h?13ffffh 098000h?09ffffh bank1 bank2 bank2 sa27 010100xxx 64/32 140000h?14ffffh 0a0000h?0a7fffh bank1 bank2 bank2 sa28 010101xxx 64/32 150000h?15ffffh 0a8000h?0affffh bank1 bank2 bank2 sa29 010110xxx 64/32 160000h?16ffffh 0b0000h?0b7fffh flash - bottom boot sector address
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 13 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 sector type f type e type d sector address size (x8) (x16) a20-a12 kb/kw address range address range bank1 bank2 bank2 sa30 010111xxx 64/32 170000h?17ffffh 0b8000h?0bffffh bank1 bank2 bank2 sa31 011000xxx 64/32 180000h?18ffffh 0c0000h?0c7fffh bank1 bank2 bank2 sa32 011001xxx 64/32 190000h?19ffffh 0c8000h?0cffffh bank1 bank2 bank2 sa33 011010xxx 64/32 1a0000h?1affffh 0d0000h?0d7fffh bank1 bank2 bank2 sa34 011011xxx 64/32 1b0000h?1bffffh 0d8000h?0dffffh bank1 bank2 bank2 sa35 011100xxx 64/32 1c0000h?1cffffh 0e0000h?0e7fffh bank1 bank2 bank2 sa36 011101xxx 64/32 1d0000h?1dffffh 0e8000h?0effffh bank1 bank2 bank2 sa37 011110xxx 64/32 1e0000h?1effffh 0f0000h?0f7fffh bank1 bank2 bank2 sa38 011111xxx 64/32 1f0000h?1fffffh 0f8000h?0fffffh bank2 bank2 bank2 sa39 100000xxx 64/32 200000h?20ffffh 100000h?107fffh bank2 bank2 bank2 sa40 100001xxx 64/32 210000h?21ffffh 108000h?10ffffh bank2 bank2 bank2 sa41 100010xxx 64/32 220000h?22ffffh 110000h?117fffh bank2 bank2 bank2 sa42 100011xxx 64/32 230000h?23ffffh 118000h?11ffffh bank2 bank2 bank2 sa43 100100xxx 64/32 240000h?24ffffh 120000h?127fffh bank2 bank2 bank2 sa44 100101xxx 64/32 250000h?25ffffh 128000h?12ffffh bank2 bank2 bank2 sa45 100110xxx 64/32 260000h?26ffffh 130000h?137fffh bank2 bank2 bank2 sa46 100111xxx 64/32 270000h?27ffffh 138000h?13ffffh bank2 bank2 bank2 sa47 101000xxx 64/32 280000h?28ffffh 140000h?147fffh bank2 bank2 bank2 sa48 101001xxx 64/32 290000h?29ffffh 148000h?14ffffh bank2 bank2 bank2 sa49 101010xxx 64/32 2a0000h?2affffh 150000h?157fffh bank2 bank2 bank2 sa50 101011xxx 64/32 2b0000h?2bffffh 158000h?15ffffh bank2 bank2 bank2 sa51 101100xxx 64/32 2c0000h?2cffffh 160000h?167fffh bank2 bank2 bank2 sa52 101101xxx 64/32 2d0000h?2dffffh 168000h?16ffffh bank2 bank2 bank2 sa53 101110xxx 64/32 2e0000h?2effffh 170000h?177fffh bank2 bank2 bank2 sa54 101111xxx 64/32 2f0000h?2fffffh 178000h?17ffffh bank2 bank2 bank2 sa55 110000xxx 64/32 300000h?30ffffh 180000h?187fffh bank2 bank2 bank2 sa56 110001xxx 64/32 310000h?31ffffh 188000h?18ffffh bank2 bank2 bank2 sa57 110010xxx 64/32 320000h?32ffffh 190000h?197fffh bank2 bank2 bank2 sa58 110011xxx 64/32 330000h?33ffffh 198000h?19ffffh flash - bottom boot sector address continued:
14 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 sector type f type e type d sector address size (x8) (x16) a20-a12 kb/kw address range address range bank2 bank2 bank2 sa59 110100xxx 64/32 340000h?34ffffh 1a0000h?1a7fffh bank2 bank2 bank2 sa60 110101xxx 64/32 350000h?35ffffh 1a8000h?1affffh bank2 bank2 bank2 sa61 110110xxx 64/32 360000h?36ffffh 1b0000h?1b7fffh bank2 bank2 bank2 sa62 110111xxx 64/32 370000h?37ffffh 1b8000h?1bffffh bank2 bank2 bank2 sa63 111000xxx 64/32 380000h?38ffffh 1c0000h?1c7fffh bank2 bank2 bank2 sa64 111001xxx 64/32 390000h?39ffffh 1c8000h?1cffffh bank2 bank2 bank2 sa65 111010xxx 64/32 3a0000h?3affffh 1d0000h?1d7fffh bank2 bank2 bank2 sa66 111011xxx 64/32 3b0000h?3bffffh 1d8000h?1dffffh bank2 bank2 bank2 sa67 111100xxx 64/32 3c0000h?3cffffh 1e0000h?1e7fffh bank2 bank2 bank2 sa68 111101xxx 64/32 3d0000h?3dffffh 1e8000h?1effffh bank2 bank2 bank2 sa69 111110xxx 64/32 3e0000h?3effffh 1f0000h?1f7fffh bank2 bank2 bank2 sa70 111111xxx 64/32 3f0000h?3fffffh 1f8000h?1fffffh note: the address range is a20:a-1 in byte mode (i/of=v il ) or a20:a0 in word mode (i/of=v ih ). the bank address bits are a20?a18 for type d, a20 and a19 for type e, and a20 for type f. flash - bottom boot security sector addresses device sector address size (x8) (x16) a20-a12 kb/kw address range address range type f type e type d 000000xxx 256/128 000000h-0000ffh 00000h-0007fh flash - bottom boot sector address continued:
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 15 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 sector group a20 a19 a18 a17 a16 a15 a14 a13 a12 sectors sga0 000000xxx sa0 01 sga1 000010xxx sa1 to sa3 11 sga2 0001 xxxxx sa4 to sa7 sga3 0010 xxxxx sa8 to sa11 sga4 0011 xxxxx sa12 to sa15 sga5 0100 xxxxx sa16 to sa19 sga6 0101 xxxxx sa20 to sa23 sga7 0110 xxxxx sa24 to sa27 sga8 0111 xxxxx sa28 to sa31 sga9 1000 xxxxx sa32 to sa35 sga10 1001 xxxxx sa36 to sa39 sga11 1010 xxxxx sa40 to sa43 sga12 1011 xxxxx sa44 to sa47 sga13 1100 xxxxx sa48 to sa51 sga14 1101 xxxxx sa52 to sa55 sga15 1110 xxxxx sa56 to sa59 00 sga16 111101xxx sa60 to sa62 10 sga17 111111000 sa63 sga18 111111001 sa64 sga19 111111010 sa65 sga20 111111011 sa66 sga21 111111100 sa67 sga22 111111101 sa68 sga23 111111110 sa69 sga24 111111111 sa70 sector group address (type a, type b, type c) (top boot block)
16 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 sector group a20 a19 a18 a17 a16 a15 a14 a13 a12 sectors sga0 000000000 sa0 sga1 000000001 sa1 sga2 000000010 sa2 sga3 000000011 sa3 sga4 000000100 sa4 sga5 000000101 sa5 sga6 000000110 sa6 sga7 000000111 sa7 01 sga8 000010xxx sa8 to sa10 11 sga9 0001x xxxx sa11 to sa14 sga10 0010 xxxxx sa15 to sa18 sga11 0011 xxxxx sa19 to sa22 sga12 0100 xxxxx sa23 to sa26 sga13 0101 xxxxx sa27 to sa30 sga14 0110 xxxxx sa31 to sa34 sga15 0111 xxxxx sa35 to sa38 sga16 1000xx xxx sa39 to sa42 sga17 1001xx xxx sa43 to sa46 sga18 1010xx xxx sa47 to sa50 sga19 1011xx xxx sa51 to sa54 sga20 1100xx xxx sa55 to sa58 sga21 1101xx xxx sa59 to sa62 sga22 1110xx xxx sa63 to sa66 00 sga23 111101 xxx sa67 to sa69 10 sga24 111111 xxx sa70 sector group address (type d, type e, type f) (bottom boot block)
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 17 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 flash memory autoselect codes note: 1. a?1 is used for byte mode. 2. output 01h at protected sector address and output 00h at unprotected sector address. type a 12 to a 19 a 6 a 1 a 0 a ?1(1) code (hex) manufacturer?s code x vil vil vil vil 04h type a byte x vil vil vih vil 55h word x vil vil vih x 2255h type d byte x vil vil vih vil 56h word x vil vil vih x 2256h type b byte x vil vil vih vil 50h word x vil vil vih x 2250h type e byte x vil vil vih vil 53h word x vil vil vih x 2253h type c byte x vil vil vih vil 5ch word x vil vil vih x 225ch type f byte x vil vil vih vil 5fh word x vil vil vih x 225fh sector group protect sector vil vih vil vil 01h (1) group address
18 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 flash memory command definitions note: *1: both read/reset commands are functionally equivalent, resetting the device to the read mode. *2: this command is valid during fast mode. *3: this command is valid while reset=vid. *4: the valid address is a0 to a6. *5: this command is valid during hi-rom mode. *6: the data ?00h? is also acceptable.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 19 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 type m, type n, type p, type q (bottom boot type) word mode: 000000h to 007fffh byte mode: 000000h to 00ffffh hrba = bank address of the hidden-rom area type h, type j, type k, type l (top boot type) : a15 = a16 = a17 = a18 = a19 = 1 type m, type n, type p, type q (bottom boot type) : a15 = a16 = a17 = a18 = a19 = 0 rd = data read from location ra during read operation. pd = data to be programmed at location pa. sd = sector protection verify data. output 01h at protected sector addresses and output 00h at unprotected sector addresses. the system should generate the following address patterns; word mode : 555h or 2aah to addresses a0 to a10 byte mode : aaah or 555h to addresses a?1 and a0 to a10 ddress bits a11 to a19 = x = ?h? or ?l? for all address commands except for program address (pa), sector address (sa),and bank address (ba). bus operations are defined in ?device bus operations?. ra = address of the memory location to be read pa = address of the memory location to be programmed addresses are latched on the falling edge of the write pulse. sa = address of the sector to be erased. the combination of a19 , a18 , a17 , a16 , a15 , a14 , a13 , and a12 will uniquely select any sector. ba = bank address (a15 to a20 ) spa = sector group address to be protected. set sector group address (sga) and (a6 , a1 , a0 ) = (0, 1, 0). hra= address of the hidden-rom area type h, type j, type k, type l (top boot type) word mode: 0f8000h to 0fffffh byte mode: 1f0000h to 1fffffh
20 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 mcp absolute maximum ratings (1,2,3) symbol parameter value unit t bias temperature under bias ?40 to +85 c t stg storage temperature ?55 to +125 c p d power dissipation 1.6 w i out output current (per i/o) 100 ma v in , v out voltage relative to gnd for data, ?0.3 to v cc f + 0.3 v address and control pins -0.2 to v cc s + 0.3 v v in reset (5) -0.5 to +13.0 v v in wp /acc (6) -0.5 to +10.5 v v cc f/v cc s voltage on vcc supply relatiive to gnd (4) ?0.3 to 3.6 v notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operati onal sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. this device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. this device contains circuitry that will ensure the output devices are in high-z at power up. 4. minimum dc voltage on input or i/o pins is ?0.3 v. during voltage transitions, input or i/o pins may undershoot vss to ?2.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc f+0.3 v or v cc s+0.3 v. during voltage transitions, input or i/o pins may overshoot to v cc f+2.0 v or v cc s+2.0 v for periods of up to 20 ns. 5. minimum dc input voltage on reset pin is ?0.5 v. during voltage transitions, reset pin may undershoot vss to ?2.0 v for per iods of up to 20 ns. voltage difference between input and supply voltage (v in -v cc f or v cc s) does not exceed 9.0 v. maximum dc input voltage on reset pin is +13.0 v which may overshoot to +14.0 v for periods of up to 20 ns. 6. minimum dc input voltage on wp /acc pin is ?0.5 v. during voltage transitions, wp /acc pin may undershoot vss to ?2.0 v for periods of up to 20 ns. maximum dc input voltage on wp /acc pin is +10.5 v which may overshoot to +12.0v for periods of up to 20 ns, when v cc f is applied.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 21 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 mcp operating range range ambient temperature v ccf ,v ccs industrial ?40c to +85c 2.7?3.3v capacitance (1,2) symbol parameter cond itions typ. max. unit c in input capacitance v in = 0v 11 14 pf c in 2 input capacitance v in = 0v 12 16 pf c in 3 input capacitance v in = 0v 14 16 pf c out input/output capacitance v out = 0v 21.5 26 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c, f = 1 mhz standard voltage range: v cc = 2.7-3.3 v f lash m emory sram u nits max access time 70 85 70 ns ce access 70 85 70 ns oe access 30 40 35 ns
22 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 flash dc characteristics symbol parameter test conditions min. max. unit i li input leakage v in =v ss to v cc f, v cc s -1.0 1.0 a i lo output leakage v out =v ss to v cc f, v cc s -1.0 1.0 a i lit reset inputs v cc f=v cc f max., v cc s=v cc s max. ? 35 a leakage current reset = 12.5v i lia acc inputs v cc f=v cc f max., v cc s=v cc s max. ? 20 a leakage current wp /acc = vacc max. i cc 1f flash vcc (1) ce f=v il tcycle = 5mhz byte ? 16 ma active current (read) oe =v ih tcycle = 5mhz word ? 18 tcycle = 1mhz byte ? 7 tcycle = 1mhz word ? 7 i cc 2f flash vcc active (2) ce f=v il ?35ma current(program/erase) oe =v ih i cc 3f flash vcc active (2) ce f=v il byte ? 51 ma current oe =v ih word 53 (read-while-program) i cc 4f flash vcc active (5) ce f=v il byte ? 51 ma current oe =v ih word 53 (read-while-erase) i cc 5f flash vcc active (5) ce f=v il ?35ma current oe =v ih (read-while-erase) i sb 1f flash vcc v cc f = vcc max, ce f= v cc f = + 0.3v ? 1 5 a standby current reset, ce f, wp /acc = v cc f = + 0.3v i sb 2f flash vcc v cc f = vcc max, reset = v ss = + 0.3v ? 1 5 a standby current wp /acc = v cc f = + 0.3v ( reset ) i sb 3f flash vcc (3) v cc f = vcc max. ce f, = v ss = + 0.3v ? 1 5 a standby current reset, wp /acc = v cc f = + 0.3v (auto sleep mode)v in = v cc f + 0.3v or v ss + 0.3v
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 23 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 notes: 1. the icc current listed includes both the dc operating current and the frequency dependent component. 2. icc active while embedded algorithm (program or erase) is in progress. 3. automatic sleep mode enables the low power mode when address remain stable for 150 ns. 4. applicable for only v cc f applying. 5. embedded algorithm (program or erase) is in progress. (@5 mhz) 6. v cc indicates lower of v cc f or v cc s . symbol parameter test conditions min. max. unit v il input low level -0.2 0.5 v v ih input high level 2.4 v cc + 0.3 (6) v v id voltage for sector 11.5 12.5 v protection, and temporary sector unprotection ( reset ) (4) v acc voltage for program 8.5 9.5 v acceleration ( wp /a cc ) (4) v ol output low level v cc f = v cc f min., v ccs =v ccs min. ? 0.4 v i ol = 1.0ma v oh output high level v cc f = v cc f min., v ccs =v ccs min. 2.4 ? v i ol = 1.0ma v lko flash low vccf 2.3 2.5 v flash dc characteristics continued:
24 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 symbol v alue parameter jedec standard t est setup min unit ce recover time _ t ccr _0ns ac characteristics - ce timing timing diagram for alternating sram to flash
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 25 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 flash read only switching characteristics (over operating range) symbol p arameter min. max. min. max. unit t kc cycle time 70 85 ? ns t acc address to output delay ? 70 ? 85 ns t ce chip enable to output delay ? 70 ? 85 ns t oe output enable to output delay ? 30 ? 35 ns t df chip enable to output high-z ? 30 ? 30 ns t df output enable to output high-z ? 30 ? 30 ns t oh output hold time from addresses, 0 ? 0 ? ns ce f or oe , whichever occurs first t ready reset pin low to read mode ? 20 ? 20 s flash ac test conditions parameter unit input pulse level 0v to 3.0v input rise and fall times 5 ns input and output timing 1.5v and reference level output load 1 ttl gate and 30pf
26 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 flash read cycle
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 27 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 note: 1. this does not include the preprogramming time. flash erase/program operation characteristics (over operating range) -70 ns -85ns symbol p arameter min. max. min. max. unit t wc write cycle time 70 - 85 - ns t as address setup time ( we to addr.) 0 - 0 - ns t aso address setup time to ce f low during 15 - 15 - ns toggle bit polling t ah address hold time ( we to addr.) 45 - 45 - ns t aht address hold time from ce f or 0 - 0 - ns oe high during toggle bit polling t ds data setup time 35 - 45 - ns t dh data hold time 0 - 0 - ns t oes output enable setup time 0 - 0 - ns t oeh output enable hold time read 0 - 0 - ns t oeh output enable hold time 10 - 10 - ns toggle and data polling t ceph ce f high during toggle bit polling 20 - 20 - ns t oeph oe high during toggle bit polling 20 - 20 - ns t ghel read recover time before write ( oe to ce f) 0 - 0 - ns t ghwl read recover time before write ( oe to we )0-0-ns t ws we setup time (cef to we) 0 - 0 - ns t cs ce f setup time (we to cef) 0 - 0 - ns t wh we hold time (cef to we) 0 - 0 - ns t ch ce f hold time (we to cef) 0 - 0 - ns t wp write pulse width 30 - 35 - ns t cp ce f pulse width 30 - 35 - ns t wph write pulse width high 30 - 30 - ns t cph ce f pulse width high 30 - 30 - ns t whwh 1 byte programming operation - 12 - 15 s t whwh 1 word programming operation - 15 - 20 s t whwh 2 sector erase operation (1) - 0.7 - 1 s t vcs v cc f setup time 50 - 50 - s
28 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 note: 2. this timing is for sector protection operation. 3. the time between writes must be less than ?ttow ? otherwise that command will not be accepted and erasure will start. a time-out or ?ttow ? from the rising edge of last ce f or we whichever happens first will initiate the execution of the sector erase command(s). 4. when the erase suspend command is written during the sector erase operation, the device will take a maximum of ?tspd ? to suspend the erase operation. flash erase/program operation characteristics continued (over operating range) -70 ns -85ns symbol p arameter min. max. min. max. unit t vlht voltage transition time (2) 4- 4 - s t vidr rise time to v id (2) 500 - 500 - ns t vacca rise time to v acc 500 - 500 - ns t rb recovery time from ry/ by 0- 0 - ns t rp reset pulse width 500 - 500 - ns t eoe delay time from embedded output enable - 70 - 85 ns t rh reset high level period before read 100 - 200 - ns t busy program/erase valid to ry/b y delay - 75 - 90 ns t tow erase time-out time (3) 50 - 50 - s t spd erase suspend transition time (4) - 20 -20 s
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 29 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 flash write cycle (we control) notes: 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte address. 3. dq7 is the output of the complement of the data written to the device. 4. dout is the output of the data written to the device. 5. figure indicates last two bus cycles out of four bus cycle sequence. 6. these waveforms are for the 16 mode (the addresses differ from 8 mode).
30 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 flash write cycle (cef control) notes: 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte address. 3. dq7 is the output of the complement of the data written to the device. 4. dout is the output of the data written to the device. 5. figure indicates last two bus cycles out of four bus cycle sequence. 6. these waveforms are for the 16 mode (the addresses differ from 8 mode).
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 31 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 flash ac waveforms chip/sector erase operations *sa is the sector address for sector erase. address = 555h for chip erase. note: these waveforms are for the 16 mode (the addresses differ from 8 mode).
32 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 flash ac waveforms for data poling during embedded alogrithm operations *dq7 = valid data (the device has completed the embedded operation.)
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 33 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 flash ac waveforms for toggle bit during embedded algorithm operations * dq6 stops toggling (the device has completed the embedded operation).
34 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 flash back-to-back read/write timing diagram note: this is example of read for bank 1 and embedded algorithm (program) for bank 2. ba1: address of bank 1. ba2: address of bank 2.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 35 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 flash ry/by timing diagram during write/erase operations flash ry/ timing diagram
36 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 flash temporary sector group unprotection
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 37 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 flash extended sector group protection sgax: sector group address to be protected sgay : next group sector address to be protected time-out : time-out window = 250 s (min.)
38 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 flash accelerated program
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 39 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 sram read cycle switching characteristics (1) (over operating range) 70 ns symbol parameter min. max. unit t rc read cycle time 70 ? ns t aa address access time ? 70 ns t oha output hold time 10 ? ns t ace1 ce1 s access time ? 70 ns t doe oe access time ? 35 ns t hzoe (2) oe to high-z output ? 25 ns t lzoe (2) oe to low-z output 5 ? ns t hzce1 (2) ce1 s to high-z output 0 25 ns t lzce1 (2) ce1 s to low-z output 10 ? ns t ba lb s , ub s access time ? 70 ns t hzb lb s , ub s to high-z output 0 25 ns t lzb lb s , ub s to low-z output 0 ? ns notes: 1. test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9v, input pulse levels of 0.4 to 1.4v and output loading specified in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. sram power supply characteristics (1) (over operating range) symbol parameter test conditions min. max. unit i cc vcc dynamic operating v ccs = max., com. ? 20 ma supply current i out = 0 ma, f = f max ind. ? 25 i cc 1 operating supply v ccs = max., com. ? 3 ma current i out = 0 ma, f = 0 ind. ? 3 i sb 1 ttl standby current v ccs = max., com. ? 0.3 ma (ttl inputs) v in = v ih or v il ind. ? 0.3 ce1 s = v ih , ce2 s = v il , f = 1 mh z or ulb control v ccs = max., v in = v ih or v il ce1 s = v il , f = 0, ub s = v ih , lb s = v ih i sb 2 cmos standby v ccs = max., com. ? 15 a current (cmos inputs) ce1 s v ccs ? 0.2v, ind. ? 15 ce2 s 0.2v, v in v ccs ? 0.2v, or v in 0.2v, f = 0 or ulb control v ccs = max., ce1 s = v il v in 0.2v, f = 0; ub s / lb s = v ccs ? 0.2v note: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
40 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 sram ac test conditions parameter unit input pulse level 0.4v to 2.2v input rise and fall times 5 ns input and output timing v ref and reference level output load see figures 1 and 2 sram ac test loads figure 1 figure 2 3070 ? 30 pf including jig and scope 3150 ? output 1.8v 2.7v - 3.3v r1( ?) 3070 r2( ?) 3150 v ref 1.5v v tm 2.8v r1 5 pf including jig and scope r2 output vtm
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 41 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 data valid previous data valid t aa t oha t oha t rc d out address ac waveforms sram read cycle no. 1 (1,2) (address controlled) ( ce1 s = oe = v il , s or s = v il ) ac waveforms sram read cycle no. 2 (1,3) ( ce1 s , oe , and ub s / lb s controlled) notes: 1. we is high for a read cycle. 2. the device is continuously selected. oe , ce1 , ub s , or lb s = v il . 3. address is valid prior to or coincident with ce1 low transition. t rc t oha t aa t doe t lzoe t ace1/ t ace2 t lzce1/ t lzce2 t hzoe high-z data valid t hzce1 address oe ce1 s ce2 s dout lb s , ub s t hzb t ba t lzb
42 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 write cycle switching characteristics (1,2) (over operating range) 70 ns symbol parameter min. max. unit t wc write cycle time 70 ? ns t sce1 ce1 s to write end 60 ? ns t aw address setup time to write end 60 ? ns t ha address hold from write end 0 ? ns t sa address setup time 0 ? ns t pwb lb s , ub s valid to end of write 60 ? ns t pwe we pulse width 50 ? ns t sd data setup to write end 30 ? ns t hd data hold from write end 0 ? ns t hzwe (3) we low to high-z output ? 20 ns t lzwe (3) we high to low-z output 5 ? ns notes: 1. test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9v, input pulse levels of 0.4v t o 1.4v and output loading specified in sram ac test loads: figure 1 2. the internal write time is defined by the overlap of ce1 low and ub or lb , and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the signal that termi nates the write. 3. tested with the load in sram ac test loads: figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. notes: 1. write is an internally generated signal asserted during an overlap of the low states on the ce1 s and we inputs and at least one of the lb s and ub s inputs being in the low state. 2. write = ( ce1 s ) [ ( lb s ) = ( ub s ) ] ( we ). ac waveforms sram write cycle no. 1 (1,2) ( s controlled, oe = high or low) data-in valid data undefined t wc t sce1 t sce2 t aw t ha t pwe (4) t hzwe high-z t lzwe t sa t sd t hd address ce1 s ce2 s we dout din lb s , ub s
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 43 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 sram write cycle no. 2 ( we controlled: oe is high during write cycle) sram write cycle no. 3 ( we controlled: oe is low during write cycle) data-in valid data undefined t wc t sce1 t sce2 t aw t ha t pwe1, 2 t hzwe high-z t lzwe t sa t sd t hd address oe ce1s ce2s we lbs , ubs dout din data-in valid data undefined t wc t sce1 t sce2 t aw t ha t pwe1, 2 t hzwe high-z t lzwe t sa t sd t hd address oe ce1s ce2s we lbs , ubs dout din
44 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 sram data retention switching characteristics symbol p arameter test condition min. max. unit v dr vcc for data retention see data retention waveform 1.0 3.3 v i dr data retention current vcc = 1.0v, cs1 vcc ? 0.2v ? 15 a t sdr data retention setup time see data retention waveform 0 ? ns t rdr recovery time see data retention waveform t rc ?ns sram data retention waveform ( ce1 controlled) write cycle no. 4 ( ub s / lb s controlled, ce1 s is low, ce2s is high) data undefined t wc address 1 address 2 t wc high-z t pbw word 1 word 2 t hd t sa t hzwe address ubs , lbs we d out d in oe data in valid t lzwe t sd t pbw data in valid t sd t hd t sa t ha t ha ub_cswr4.eps v cc ce1 s v cc - 0.2v t sdr t rdr v dr ce1 s gnd 1.65v 1.4v data retention mode
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 45 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 symbol min. typ. max. units a? ?1.40mm a1 0.28 0.38 0.48 mm d 11.50 11.60 11.70 mm d1 ? 8.80 ? mm e 7.90 8.00 8.10 mm e1 ? 7.20 ? mm e ? 0.80 ? mm 10 9 8 7 6 5 4 3 2 1 1 2 3 4 5 6 7 8 9 10 a b c d e f g h j k l m a b c d e f g h j k l m ? 0.45 + 0.10/?0.05 (73x) e e a1 seating plane e dd1 e1 a mini ball grid array ? 73-ball bga (32 mb flash and 8 mb sram) package code: b ( 8 mm x 11.60 mm body, 0.8 mm ball pitch )
46 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 part number logic is 71 x xx f xx x s xx ? xxxx x x issi prefix product family: flash/sram mcp voltage : v = 3.0 center voltage sram data bus width: 08, 16, or pc (pin configurable) flash label flash density (mbit) flash organization : a = type a - top boot block (bank1: 4mb, bank2: 28mb) b = type b - top boot block (bank1: 8mb, bank2: 24mb) c = type c - top boot block (bank1: 16mb, bank2: 16mb) d = type d - bottom boot block (bank1: 4mb, bank2: 28mb) e = type e - bottom boot block (bank1: 8mb, bank2: 24mb) f = type f - bottom boot block (bank1: 16mb, bank2: 16mb) g = user configurable bank grouping sram label sram density (mbit) speed : 8570 = 85ns flash, 70ns sram 7070 = 70ns flash, 70ns sram 8585 = 85ns flash, 85ns sram 7085 = 70ns flash, 85ns sram package: a = 101-ball bga b = 73-ball bga f = 69-ball bga temperature grade: blank = commercial i = industrial
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 47 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 sram data boot flash bank flash sram order part no. bus section organization sp eed(ns)speed(ns) package is71v08f32as08-7070bi 8 top 4mb, 28mb 70 70 73-ball bga is71v08f32bs08-7070bi 8 top 8mb, 24mb 70 70 73-ball bga is71v08f32cs08-7070bi 8 top 16mb, 16mb 70 70 73-ball bga is71v08f32ds08-7070bi 8 bottom 4mb, 28mb 70 70 73-ball bga is71v08f32es08-7070bi 8 bottom 8mb, 24mb 70 70 73-ball bga is71v08f32fs08-7070bi 8 bottom 16mb, 16mb 70 70 73-ball bga is71v08f32as08-7085bi 8 top 4mb, 28mb 70 85 73-ball bga is71v08f32bs08-7085bi 8 top 8mb, 24mb 70 85 73-ball bga is71v08f32cs08-7085bi 8 top 16mb, 16mb 70 85 73-ball bga is71v08f32ds08-7085bi 8 bottom 4mb, 28mb 70 85 73-ball bga is71v08f32es08-7085bi 8 bottom 8mb, 24mb 70 85 73-ball bga IS71V08F32FS08-7085BI 8 bottom 16mb, 16mb 70 85 73-ball bga is71v08f32as08-8570bi 8 top 4mb, 28mb 85 70 73-ball bga is71v08f32bs08-8570bi 8 top 8mb, 24mb 85 70 73-ball bga is71v08f32cs08-8570bi 8 top 16mb, 16mb 85 70 73-ball bga is71v08f32ds08-8570bi 8 bottom 4mb, 28mb 85 70 73-ball bga is71v08f32es08-8570bi 8 bottom 8mb, 24mb 85 70 73-ball bga is71v08f32fs08-8570bi 8 bottom 16mb, 16mb 85 70 73-ball bga is71v08f32as08-8585bi 8 top 4mb, 28mb 85 85 73-ball bga is71v08f32bs08-8585bi 8 top 8mb, 24mb 85 85 73-ball bga is71v08f32cs08-8585bi 8 top 16mb, 16mb 85 85 73-ball bga is71v08f32ds08-8585bi 8 bottom 4mb, 28mb 85 85 73-ball bga is71v08f32es08-8585bi 8 bottom 8mb, 24mb 85 85 73-ball bga is71v08f32fs08-8585bi 8 bottom 16mb, 16mb 85 85 73-ball bga is71v16f32as08-7070bi 1 6 top 4mb, 28mb 70 70 73-ball bga is71v16f32bs08-7070bi 1 6 top 8mb, 24mb 70 70 73-ball bga is71v16f32cs08-7070bi 16 top 16mb, 16mb 70 70 73-ball bga is71v16f32ds08-7070bi 16 bottom 4mb, 28mb 70 70 73-ball bga is71v16f32es08-7070bi 1 6 bottom 8mb, 24mb 70 70 73-ball bga is71v16f32fs08-7070bi 16 bottom 16mb, 16mb 70 70 73-ball bga
48 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00b 05/23/02 is71v08f32 x s08, is71v16f32 x s08 ordering information industrial range: -40oc to +85oc sram data boot flash bank flash sram order part no. bus section organizatio n speed(ns)speed(ns) package is71v16f32as08-7085bi 16 top 4mb, 28mb 70 85 73-ball bga is71v16f32bs08-7085bi 16 top 8mb, 24mb 70 85 73-ball bga is71v16f32cs08-7085bi 16 top 16mb, 16mb 70 85 73-ball bga is71v16f32ds08-7085bi 16 bottom 4mb, 28mb 70 85 73-ball bga is71v16f32es08-7085bi 16 bottom 8mb, 24mb 70 85 73-ball bga is71v16f32fs08-7085bi 16 bottom 16mb, 16mb 70 85 73-ball bga is71v16f32as08-8570bi 16 top 4mb, 28mb 85 70 73-ball bga is71v16f32bs08-8570bi 16 top 8mb, 24mb 85 70 73-ball bga is71v16f32cs08-8570bi 16 top 16mb, 16mb 85 70 73-ball bga is71v16f32ds08-8570bi 16 bottom 4mb, 28mb 85 70 73-ball bga is71v16f32es08-8570bi 16 bottom 8mb, 24mb 85 70 73-ball bga is71v16f32fs08-8570bi 16 bottom 16mb, 16mb 85 70 73-ball bga is71v16f32as08-8585bi 16 top 4mb, 28mb 85 85 73-ball bga is71v16f32bs08-8585bi 16 top 8mb, 24mb 85 85 73-ball bga is71v16f32cs08-8585bi 16 top 16mb, 16mb 85 85 73-ball bga is71v16f32ds08-8585bi 16 bottom 4mb, 28mb 85 85 73-ball bga is71v16f32es08-8585bi 16 bottom 8mb, 24mb 85 85 73-ball bga is71v16f32fs08-8585bi 16 bottom 16mb, 16mb 85 85 73-ball bga

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